Post by Christian Corti
This is wrong. The 5100/5110 has a normal microprogrammed processor
(called PALM) with a normal instruction set. Since IBM was too lazy to
program native interpreters for the PALM, they wrote simple machine
emulators (one for the S/360 and one for the S/3) in machine language,
not microcode. They thought that this would be easier...
http://www.garlic.com/~lynn/2015c.html#42 John Titor was right? IBM 5100
My view is that it is semantics ... native processor programming used to
emulate another architecture tended to be called microcode. when I was
working on cp67 ... i use to refer to cp67 as the microcode of the
I did some amount of work with the guy at PASC that did the 370/145 APL
assist "microcode" (and other native processor programming, especially
related to 370 emulation) ... I was at sister location on the other
coast in cambridge CSC ... some past posts
One such is that endicott roped me into helping with ECPS that would
come out for 138/148 (followon to 135/145). They had 6k bytes available
for ECPS (native) programming ... and wanted to choose the 6k bytes of
kernel instructions to move into native processor language (microcode)
... aka moved from 370 to native on nearly byte-for-byte basis.
Two approaches were used to select the 6k bytes of instructions. One was
instruction hotspot ... a table of counters representing 32bytes of
kernel addresses was created in the 370/145 microcode ... and
(microcode) routine was added that periodically sampled the current
(kernel) instruction address and increment the corresponding address.
there was kernel modification that created time-stamps at entry and exit
of various routines and calculate the elapsed time since the previous
time-stamp. subpaths within routine could be calculated between points
that other routines were called. Old post with results from runs that
were used to select kernel codepaths for translation into "microcode":
http://www.garlic.com/~lynn/94.html#21 370 ECPS VM microcode assist
the 370 emulator "microcode" had typical avg of ten native instructions
per 370 instructions ... so the 6k bytes of 370 instructions accounting
for 79.55% of time spent in kernel execution ... when moved into 6k
bytes of native instructions ... it ran ten times faster.
the "vertical" native programming instruction of low-end & mid-range
microprocessors looked very much like machine programming. The high-end
370s were horizontal microprogramming ... which was more like lots of
bits that activated/started various hardware operations ... that could
run in parallel. Instead of being characterized as avg. number of
(vertical) native instructions per 370 instruction ... they were
characterized as avg. machine cycles per 370 instruction. The 370/165
was 2.1 machine cycles per 370 instruction ... but was improved for
370/168 to 1.6 machine cycles per 370 instruction ... and then improved
to one machine cycle per 370 instruction for 3033.
I've mentioned before that during FS period, internal 370 efforts were
being killed off and the lack of 370 products during this period allowed
clone processors to gain market foothold
when FS imploded ... there was mad rush to get products back into the
370 pipeline and 3033 and 3081 were kicked off in paralle. 3033 started
out Q&D remap of 168 logic to 20% faster chips ... however tweaks done
along the way (like reducing avg. machine cycles per 370 instruction)
got 3033 up to 1.5 times 168. this has discussion of FS and how poorly
the 3033 & 3081 compared to clone competition:
The 3033 started doing minor microcode feature tweaks with the kernel
software not running unless those features were available (by
comparison, the ECPS kernel code dynamically determined whether ECPS was
available or not and adapt accordingly, running on machines with or w/o
the microcode tweaks). The 3033 wanted to offer something similar to
ECPS on their machine ... but since the 3033 was already running at one
machine cycler per 370 instruction ... it was difficult to show any
performance improvement using that approach (and because of various
reasons could even run slower).
The high-end clone processor competition reacted to this frequent
microcode feature changes/tweaks with "macro-code" ... approximately a
special state for 370-like instructions ... which was much easier to
change/program than native horizontal microcode. Later this was then
used to implement a special hardware hypervisor (basically a subset of
virtual machine functions). It took significant time & effort for 3090
to react to this competition with PR/SM ... since it all had to be done
(in the much more difficult) native horizontal "microcode".
disclaimer: I had transferred from CSC to SJR in san jose and was
regular at monthly baybunch meetings. I did a series of presentations at
baybunch on how ECPS was done. the people in the audience that were
working on hypervisor with macrocode in the audience were asking loads
of questions (hypervisor hadn't been announced yet).
some past posts mentioning PR/SM and/or macrocode
http://www.garlic.com/~lynn/2013.html#3 Is Microsoft becoming folklore?
http://www.garlic.com/~lynn/2013.html#58 Was MVS/SE designed to confound Amdahl?
http://www.garlic.com/~lynn/2013.html#69 What is a Mainframe?
http://www.garlic.com/~lynn/2013f.html#68 Linear search vs. Binary search
http://www.garlic.com/~lynn/2013i.html#36 The Subroutine Call
http://www.garlic.com/~lynn/2013l.html#27 World's worst programming environment?
http://www.garlic.com/~lynn/2013n.html#46 'Free Unix!': The world-changing proclamation made30yearsagotoday
http://www.garlic.com/~lynn/2013n.html#62 'Free Unix!': The world-changing proclamation made30yearsagotoday
http://www.garlic.com/~lynn/2014b.html#80 CPU time
http://www.garlic.com/~lynn/2014b.html#82 CPU time
http://www.garlic.com/~lynn/2014d.html#17 Write Inhibit
http://www.garlic.com/~lynn/2014d.html#20 Write Inhibit
http://www.garlic.com/~lynn/2014e.html#39 Before the Internet: The golden age of online services
http://www.garlic.com/~lynn/2014f.html#78 Over in the Mainframe Experts Network LinkedIn group
http://www.garlic.com/~lynn/2014i.html#90 IBM Programmer Aptitude Test
http://www.garlic.com/~lynn/2014j.html#10 R.I.P. PDP-10?
http://www.garlic.com/~lynn/2014j.html#19 DG Nova 1200 as console
http://www.garlic.com/~lynn/2014j.html#100 No Internet. No Microsoft Windows. No iPods. This Is What Tech Was Like In 1984
http://www.garlic.com/~lynn/2015.html#85 a bit of hope? What was old is new again
virtualization experience starting Jan1968, online at home since Mar1970